1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to static semiconductor memory devices (referred to as SRAM hereinafter) using bipolar transistors.
2. Description of the Background Art
Semiconductor memory devices include SRAM write data which is held unless a power supply is turned off. SRAMs are classified into a MOSSRAM including MOS transistors as components and a bipolar SRAM including bipolar transistors as components. A bipolar SRAM is used as a part of which a high speed operation is required such as a central portion of a CPU (central processing unit) because the bipolar SRAM operates at a higher speed than a MOSSRAM. FIG. 7 is a schematic block diagram showing an entire arrangement of a chip of a bipolar SRAM.
Referring to FIG. 7, a bipolar SRAM 100 comprises a memory array 1, a row address buffer.multidot.decoder 2, a column address buffer.multidot.decoder 3, read/write circuit 4, a sense amplifier 5, an output buffer 6, a word line discharging circuit.multidot.holding current control circuit 7 and a read/write control circuit 8. Bipolar SRAM 100 further comprises a row address terminal T.sub.AX receiving an externally applied row address signal, a column address terminal T.sub.AY receiving an externally applied column address signal, an input data terminal T.sub.DI receiving an externally applied write data, a control terminal T.sub.CTL receiving an externally applied write control signal and a data output terminal T.sub.DO externally outputting read data.
Memory array 1 includes memory cells MCs arranged in a matrix of rows and columns, two word lines WP and WN provided for each row, and a bit line pair BP provided for each column. Each bit line pair BP includes two bit lines, BTL and BTR. The word line WN is connected to word line discharging circuit.multidot.holding current control circuit 7. Only the word line WP is connected to row address buffer.multidot.decoder 2.
The internal arrangement and a basic operation principle of the memory cell MC will be described. FIG. 8 is a circuit diagram showing the basic arrangement of a memory cell of a bipolar SRAM. With reference to FIG. 8, the memory cell MC includes two NPN type multiemitter transistors QML and QMR connected crossing with each other and loads RML and RMR. Load RML is provided between the collector of transistor QML and the word line WP corresponding to the memory cell MC. Similarly, load RMR is provided between the collector of transistor QMR and said corresponding word line WP. One emitter of transistor QML and one emitter of transistor QMR are connected in common to the other word line WN corresponding to the memory cell MC. The other emitter of transistor QML is connected to the bit line BTL corresponding to the memory cell MC. The other emitter of transistor QMR is connected to the other bit line BTR corresponding to the memory cell MC. In the following description, the word line WP is referred to as a positive word line and the word line WN is referred to as a negative word line.
Complementary potentials corresponding to data held at a node between load RML and transistor QML and a node between load RMR and transistor QMR. The node between load RML and transistor QML and that between load RMR and transistor QMR are referred to as storage nodes NL and NR, respectively, in the following.
It is assumed that a potential V.sub.NH on the positive word line WP corresponding to a logical "H" level and a potential V.sub.NL corresponding to a logical level "L" are held at storage nodes NL and NR, respectively. In reading data from the memory cell MC, the potential on the positive word line WP corresponding to the memory cell MC is raised to a high potential V.sub.H (for example -1.0 V). The bit lines BTL and BTR are connected to constant current sources IRWL and IRWR, respectively. In response to the potential rise of the word line WP, the potential at storage node NL is raised to approximately the same potential V.sub.H on the positive word line WP. At the same time, the potential at storage node NR is also raised to a fixed potential V.sub.L (for example -2.0 V) lower than the potential V.sub.H at the node NL. Bit line BTL is connected to a power supply Vcc through an NPN type transistor QRWL for reading and writing. Similarly, the other bit line BTR is connected to power supply Vcc through an NPN transistor QRWR. In a data reading, a read reference potential V.sub.RD is applied to the bases of transistors QRWL and QRWR. Read reference potential V.sub.RD is a potential close to the intermediate value (for example, about -1.6 V) between the potential V.sub.H corresponding to a H level and the potential V.sub.L corresponding to a L level. The potential V.sub.L at storage node NR and the potential V.sub. H at storage node NL are applied to the bases of transistors QML and QMR, respectively.
Since transistor QML and transistor QRWL constitute an ECL (emitter coupled logic) with respect to constant current source IRWL, transistor QRWL is rendered conductive which receives at its base the potential V.sub.RD higher than the base potential V.sub.L of transistor QML. As a result, the current flows to bit line BTL from power supply Vcc through transistor QRWL, whereby the potential on bit line BTL becomes the potential (-1.6 V-0.8 V=-2.4 V) lower than the base potential V.sub.RD of transistor QRWL by a base-emitter voltage V.sub.BE (.apprxeq.0.8 V) of the transistor. Similarly, transistors QMR and QRWR constitute an ECL with respect to constant current source IRWR. Transistor QMR receives a potential V.sub.H higher than that of storage node NL at its base. As a result transistor QMR is rendered conductive in this ECL, whereby a current flows to bit line BTR from positive word line WP at a H level potential through load RMR and transistor QMR, causing the bit line BTR to attain a low potential (-1.0 V-0.8 =-1.8 V) lower than the base potential V.sub.H of transistor QMR by the base-emitter voltage V.sub.BE of the transistor.
Conversely, when the potentials held at storage nodes NL and NR are at a L level and a H level, respectively, transistor QML is rendered conductive at bit line BTL side of the memory cell MC and transistor QRWR is rendered conductive at bit line BTR side. In this case, the potential on bit line BTL becomes -1.8 V and the potential on bit line BTR becomes -2.4 V. That is, the series-connection circuit of load RML and transistor QML constitutes an inverter IL inverting the potential at storage node NR and outputting the inversion to bit line BTL. Similarly, the series-connection circuit of load RMR and transistor QMR constitutes an inverter IR inverting the potential at storage node NL and outputting the inversion to bit line BTR. As a result, a potential difference is generated between BTL and BTR in a data reading. The potential difference is sensed by sense amplifier 5 in FIG. 7 to obtain the storage data of the selected memory cell MC.
In writing data to the memory cell MC, the potential on positive word line WP is raised to a high potential V.sub.H and complementary potentials corresponding to data to be written are applied to the bases of transistors QRWL and QRWR. It is assumed that data is already written in the memory cell MC so that the potentials at storage nodes NL and NR are at a H level and a L level, respectively. In this case, since transistors QML and QMR constitute the ECL, transistor QML is turned off and the other transistor QMR is turned on. In writing the reverse data to presently written data to the memory cell MC, that is, when the potentials at storage nodes NL and NR are inverted to a L level and a H level, respectively, the potential V.sub.WL (ordinarily -2.4 V) lower than the potential V.sub.L held at storage node NR is applied to the base of transistor QRWL and the potential V.sub.WH (ordinarily -0.8 V) higher than the potential V.sub.H held at storage node NL is applied to the base of transistor QRWR. As a result, transistor QML is switched from off to on state and transistor QRWL enters an off state. Meanwhile, transistor QMR is switched from on to off state and transistor QRWR enters an on state.
Turning-on of transistor QML causes a current to flow from positive word line WP through load RML and transistor QML to bit line BTL, thereby lowering the potential at storage node NL. Conversely, the turning-off of transistor QMR causes no current to flow from word line WP to load RMR, thereby raising the potential at storage node NR to the same potential as the potential V.sub.H on positive word line WP. At this time, a current flows to bit line BTR from power supply Vcc through transistor QRWR. As the foregoing, storage node NR is charged in response to the high potential on positive word line WP and storage node NL is discharged. The potential at storage node NR eventually becomes approximately equal to the potential V.sub.H on positive word line WP and the potential at storage node NL becomes a low level potential V.sub.L.
Conversely, in a data writing wherein storage nodes NL and NR are forced to "H" and "L" potentials, respectively, the potential V.sub.WH and the potential V.sub.WL are applied to the base of transistor QRWL and the base of the transistor QRWR, respectively. In this case, transistor QRWL receiving a high potential at its base is turned on and transistor QML is turned off. At the same time, transistor QMR receiving a high potential at its base is turned on and transistor QRWR is turned off. Therefore in this case, no change is caused in the conduction state of transistors QML and QMR, whereby the potentials held at storage nodes NL and NR remain unchanged. The data thus written (the potentials at storage nodes NL and NR) should be held even after the end of the writing. When the potentials at storage nodes NL and NR attain respectively "L" and "H" in this writing, in order to maintain the logical levels of the potentials at storage nodes NL and NR, the on state of transistor QML and the off state of transistor QMR should be maintained even after the end of the writing. Conversely, when the potentials at storage nodes NL and NR attain "H" and "L" in the writing, the off state of transistor QML and the on state of QMR should be maintained even after the end of the writing. However, since the potential on positive word line WP is lowered to the original potential V.sub.NH after the end of the writing, the base potentials of transistors QML and QMR are lowered to the original potential V.sub.NH and V.sub.NL, respectively, thereby preventing the conduction states of transistors QML and QMR from remaining the same as that in the data writing. The potentials at storage nodes NL and NR cannot be maintained when the conduction states of transistors QML and QMR change. That is, the data of the memory cell MC is damaged. Such data damage is prevented by flowing a small current all the time through negative word line WN from the memory cell MC. Negative word line WN is connected to one emitter unconnected to bit line BTL out of the two emitters of transistor QML and to one emitter unconnected to bit line BTR out of the two emitters of transistor QMR. In this method, current flows all the time from a storage node attaining a low level potential V.sub.L as a result of the writing to negative word line WN through a transistor turning on as a result of the writing out of transistors QML and QMR. Therefore, the potential at the storage node attaining a L level in the writing is maintained even after the end of the data writing. With inverters IL and IR cross-connected to each other, a maintained potential of the storage node of one inverter results in a maintained potential of the storage node of the other inverter. As a result, no storage data is damaged in the memory cell MC. As the foregoing, the current constantly flowed through negative word line WN to maintain the storage data of the memory cell MC is referred to as a data holding current. The potential on positive word line WP is raised to a H level only in the case of data writing and data reading of a memory cell connected thereto and the potential is lowered to the original level at the end of the data reading and data writing. In order to enhance the rate of a potential drop of positive word line WP, the electric charge stored in positive word line WP is extracted at a high speed through a memory cell and negative word line WN connected to the word line when the data writing and the data reading finish.
Back to FIG. 7, a row address signal applied to row address terminal T.sub.AX designates one of the positive word lines WPs in memory cell array 1, which one word line is connected to a memory cell to or from which line data is written or read. Similarly, a column address signal applied to column address terminal T.sub.AY designates one of the bit line pairs BPs in memory cell array 1, which pair is connected to a memory cell to or from which pair data is written or read. In response to the row address signal applied to row address terminal T.sub.AY, row address buffer.multidot.decoder 2 supplies a high potential V.sub.H only to the word line WP designated by the row address signal among the positive word lines WPs in memory cell array 1. In response to the column address signal applied to column address terminal T.sub.AY, column address buffer.multidot.decoder 3 selects the column designated by the column address signal among the columns corresponding to the respective bit line pairs BPs in memory array 1.
In response to a write enable signal WE applied to write control terminal T.sub.CTL, read/write control circuit 8 controls read/write circuit 4 and word line discharging circuit.multidot.holding current source 7. Write enable signal WE designates whether a data writing or a data reading should be performed for memory array 1. When write enable signal WE designates a "data writing", read/write control circuit 8 applies the input data signal D.sub.IN applied to input data terminal T.sub.DI to read/write circuit 4. Read/write circuit 4 includes write/read transistors QRWL and QRWR (see FIG. 8) provided for each bit line pair BP in memory array 1. In response to the applied input data signal D.sub.IN, read/write circuit 4 supplies such a complementary base voltage as described above to only the transistors QRWL and QRWR corresponding to the column selected by column address buffer.multidot.decoder 3 among the read/write transistors QRWL and QRWR provided corresponding to the respective bit line pairs BPs. As a result, the data is written on such a principle as described above in the memory cell (selected memory cell) provided at a crossing point between the row designated by the row address signal and the column designated by the column address signal.
When write enable signal WE designates a "data reading", read/write control circuit 8 does not accept input data signal D.sub.IN applied to input data terminal T.sub.DI. At this time, read/write circuit 4 applies, as a gate potential, the potential V.sub.RD which is the intermediate potential between the high level potential V.sub.H and the low level potential V.sub.L only to the write/read transistors QRWL and QRWR in the column selected by column address buffer.multidot.decoder 3. As a result, a potential difference is produced between the two bit lines constituting the bit line pair corresponding to the selected memory cell according to the storage data of the selected memory cell. Sense amplifier 5 senses and amplifies the potential difference to be output. Output buffer 6 buffers the signal output from sense amplifier 5, which buffered signal is provided to output data terminal T.sub.DO as the read data D.sub.OUT from the selected memory cell.
Word line discharging circuit.multidot.holding current control circuit 7 causes the holding current to flow through all the negative word lines WNs in memory array 1, while promoting the discharging of the selected word line in response to the stop of the high potential supply to the selected word line among the positive word lines WPs in memory array 1 in the data reading and the data writing.
A positive word line receiving a potential V.sub.H in a data reading or a data writing is referred to as a word line in a selected state or a selected word line hereinafter. Similarly, a bit line pair corresponding to a column selected by column address buffer.multidot.decoder 3 in a data writing and a data reading is referred to as a bit line pair in a selected state or a selected bit line pair.
FIG. 9 is a partial circuit diagram showing a specific circuit arrangement of a bipolar SRAM. The circuit system and the reading and writing method of the bipolar SRAM are disclosed in Japanese Patent Laying Open No. 60-242584, for example. FIG. 10 is a timing chart showing the operations in the data reading and the data writing of the bipolar SRAM having the arrangement shown in FIG. 9. With reference to FIGS. 9 and 10, a specific circuit operation of the bipolar SRAM will be described in detail in the following. While memory array 1 is illustrated in FIG. 9 as having four memory cells arranged in a matrix of two rows and two columns for the purpose of simplicity, it has an arrangement having more memory cells arranged in a matrix in practice.
With reference to FIG. 9, memory cells M11, M12, M21 and M22 are arranged in a matrix of two rows and two columns in memory array 1. The arrangement of each memory cell is as shown in FIG. 8. Memory cells M11 and M12 are connected in common to a positive word line WP1 and a negative word line WN1. Memory cells M21 and M22 are connected in common to a positive word line WP2 and a negative word line WN2 different from the positive word line WP1 and the negative word line WN1.
A row decoder XD includes a selection circuit XD.sub.1 for selecting/non-selecting positive word line WP1 and a selection circuit XD.sub.2 for selecting/non-selecting the other positive word line WP2.
Selection circuit XD.sub.1 includes NPN type transistors Q1 and T1 constituting an ECL, and an NPN type transistor QWD1 having a base connected to the collector of transistor Q1. The collector of transistor Q1 is connected to a power supply Vcc through a resistor RXD.sub.1 and the collectors of transistors T1 and QWD1 are directly connected to power supply Vcc. The emitter of transistor QWD1 is connected to positive word line WP1. The emitters of transistors Q1 and T1 are connected to a constant current source IXD1.
The other selection circuit XD.sub.2 has the same arrangement as that of the selection circuit XD.sub.1.
In response to an externally applied address signal, row decoder XD sets to a high potential one of a signal X1 to be applied to the base of transistor Q1 and a signal X2 to be applied to the base of transistor Q2 and sets the other signal to a low potential to select either positive word lines WP1 or WP2. A circuit operation of row decoder XD will be described.
The base potentials of transistors T1 and T2 are set to an intermediate potential VR between the high potential and the low potential. Thus, when the input signal X1 to the base of transistor Q1 attains a high potential and input signal X2 to the base of transistor Q2 attains a low potential, transistor Q1 is rendered conductive out of transistors Q1 and T1 in selection circuit XD.sub.1. Conversely, in selection circuit XD.sub.2, transistor T2 becomes conductive and transistor Q2 becomes non-conductive. The conduction of transistor Q1 causes a current to flow from power supply Vcc through resistor RXD1 and transistor Q1 to constant current source IXD1, whereby the collector potential of transistor X1 (the base potential of transistor QWD1) falls. Non-conduction of transistor Q2 prevents the current from flowing from power supply Vcc through a resistor RXD2 and transistor Q2 to a constant current source IXD2, whereby the collector potential of transistor Q2 (a base potential of a transistor QWD2) is raised in response to the output voltage of power supply Vcc, thereby rendering transistor QWD2 conductive. As a result, the potential on the other positive word line WP2 is raised to the high potential V.sub.H (-1.0 V) in response to the output voltage of power supply Vcc. Conversely, when input signal X1 attains a low potential and input signal X2 attains a high potential, transistor Q1 becomes non-conductive in selection circuit XD.sub.1, thereby raising the potential on positive word line WP1 to a high level contrary to the former case.
In memory array 1, memory cells M11 and M21 are connected in common to a pair of two bit lines BTL1 and BTR1 constituting a bit line pair BP1. Memory cells M12 and M22 are connected in common to a pair of two bit lines BTL2 and BTR2 constituting a bit line pair BP2. Provided between the bit lines BTL1 and BTR1 are two diodes DBDL1 and DBDR1 connected in anti-series. Similarly, provided between bit lines BTL2 and BTR2 are two diodes DBDL2 and DBDR2 connected in anti-series. The node between diodes DBDL1 and DBDR1 and that between diodes DBDL2 and DBDR2 are connected in common to a constant current source BTDSCS.
Bit line pairs BP1 and BP2 are connected to a bit line clamp circuit BTCL. Bit line clamp circuit BTCL fixes the potentials on the two bit lines constituting the non-selected bit line pair to the same potential.
Bit line clamp circuit BTCL includes a clamp circuit BTCL1 provided corresponding to bit line pair BP1 and a clamp circuit BTCL2 provided corresponding to bit line pair BP2.
Clamp circuit BTCL includes an NPN type transistor QBCL1 having an emitter connected to bit line BTL1 and a collector connected to power supply Vcc and an NPN type transistor QBCR1 having an emitter connected to bit line BTR1 and a collector connected to power supply Vcc. The base of transistor QBCL1 and the base of transistor QBCR1 are connected to power supply Vcc through a common resistor RBC1 and diode D.
Clamp circuit BTCL2 has the same arrangement as that of the clamp circuit BTCL1.
A read/write circuit RWb includes NPN type transistors STa1, STc1, STa2 and STc2 provided corresponding to all the bit lines BTL1, BTR1, BTL2 and BTR2, respectively in memory array 1. Read/write circuit RWb further includes NPN type transistors STb1 and STb2 respectively provided corresponding to a base node NBC1 between transistors QBCL1 and QBCR1 and a base node NBC2 between transistors QBCL2 and QBCR2. Respective transistors STa1 and STa2 are connected in series between the corresponding bit lines BTL1 and BTL2, and a constant current source IRWL. Respective transistors STc1 and STc2 are connected in series between the corresponding bit lines BTR1 and BTR2, and constant current source IRWR. Respective transistors STb1 and STb2 are connected in series between the corresponding base nodes NBC1 and NBC2 in bit line clamp circuit BTCL and a constant current source IBTCL. The base voltages of these transistors STa1, STb1, STc1, STa2, STb2 and STc2 are controlled by a column decoder YD.
Column decoder YD includes a selection circuit YD1 for selecting/non-selecting bit line pair BP1 and a selection circuit YD2 for selecting/non-selecting bit line pair BP2.
Selection circuit YD1 includes two NPN type transistors Q3 and T3 constituting an ECL and an NPN type transistor QBD1 having a base connected to the collector of transistor Q3. The collector of transistor Q3 is connected to power supply Vcc through a resistor RYDa1 and a diode DYa1. The collector of transistor T3 is connected to the diode DYa1 through a resistor RYDb1. The emitters of transistors Q3 and T3 are connected in common to a constant current source IYDa1. The collector of transistor QBD1 is directly connected to power supply Vcc. The emitter of transistor QBD1 is connected to the bases of transistors STa1, STb1 and STc1 in read/write circuit RW.sub.b and a constant current source IYDb1 through a diode DYb1.
A selection circuit YD2 has the same arrangement as that of the selection circuit YD1.
A description will be made of column decoder YD, read/write circuit RWb and bit line clamp circuit BTCL.
Column decoder YD causes one of a signal Y1 to be applied to the base of transistor Q3 and a signal Y2 to be applied to a base of a transistor Q4 to have a high potential and causes the other signal to have a lower potential, in response to an external column address signal, to select one of the bit line pairs BP1 and BP2. It is assumed, for example, that signal Y1 applied to the base of transistor Q3 is raised to a high potential and signal Y2 applied to the base of transistor Q4 is dropped to a low potential. In this case, in a selection circuit YD1, transistor Q3 out of transistors Q3 and T3 becomes conductive to generate a current flowing from power supply Vcc to diode DYa1, resistor RYDa1 and transistor Q3. As a result, the collector potential of transistor Q3 is lowered, whereby an output signal YS1 (hereinafter referred to as a bit line selecting signal) of selection circuit YD1 is lowered to turn off transistors STa1, STb1 and STc1. Consequently, the connections are electrically cut off between bit line BTL1 and constant current source IRWL, between bit line BTR1 and constant current source IRWR and between the base node NBC1 in bit line clamp circuit BTCL and constant current source IBTCL. At the same time, in selection circuit YD2, input signal Y2 is lowered to turn on transistor T4 and turn off transistor Q4, whereby the collector potential of transistor Q4 is raised in response to the output voltage of power supply Vcc to render a transistor QBD2 conductive contrary to the case of selection circuit YD1. As a result, the current is generated which flows from a diode DYb2 to the bases of transistors STa2, STb2 and STc2 provided corresponding to bit line pair BP2 in a read/write circuit RWb. That is, a bit line selecting signal YS2 from selection circuit YD2 is raised to render transistors STa2, STb2 and STc2 conductive, thereby electrically connecting bit line BTL1 to constant current source IRWL, bit line BTR2 to constant current source IRWR and base node NBC2 in bit line clamp circuit BTCL to constant current source IBTCL.
As the foregoing, when input signal Y2 to selection circuit YD2 is at a low potential, bit line pair BP2 is selectively electrically connected to constant current sources IRWL, IRWR and IBTCL. As a result, the current flows from power supply Vcc to constant current source IBTCL through diode D, a resistor RBC2 and transistor STb2, whereby the potential at base node NBC2 falls. Therefore, transistors QBCL2 and QBCR2 become nonconductive. Conversely, since no current is generated which flows to resistor RBC1, the potential at the base node NBC1 between QBCL1 and QBCR1 rises in response to the output voltage of power supply Vcc, thereby rendering transistors QBCL1 and QBCR1 conductive to supply a high potential to bit lines BTL1 and BTR1. As a result, diodes DBDL1 and DBDR1 are forward biased to become conductive, thereby short-circuiting bit line BTL1 and bit line BTR1. With the current flowing from the cathodes of diodes DBDL1 and DBDR1 maintained constant by constant current source BTDSCS, bit lines BTL1 and BTR1 are held to the same fixed potential. That is, in this case bit line pair BP1 is not selected and bit line pair BP2 is selected.
Conversely, when input signal Y1 to selection circuit YD1 attains a low potential and input signal Y2 to selection circuit YD2 attains a high potential, signal YS1 applied to the bases of transistors STa1, STb1 and STc1 provided corresponding to bit line pair BP1 attains a high potential. At the same time, signal YS2 applied to the bases of transistors STa2, STb2 and STc2 provided corresponding to bit line pair BP2 attains a low potential. Consequently, in this case, bit line pair BP1 is selected and bit line pair BP2 is not selected.
Read/write circuit RWb further includes reading and writing transistors QRWL1 and QRWR1 provided corresponding to bit line pair BP1 and reading and writing transistors QRWL2 and QRWR2 provided corresponding to bit line pair BP2. Transistors QRWL1 and QRWR1 are provided between power supply Vcc and, bit line BTL1 and bit line BTR1, respectively, which bit lines constituting bit line pair BP1. Similarly, transistors QRWL2 and QRWR2 are provided between power supply Vcc and, bit line BTL2 and bit line BTR2, respectively, which bit lines constituting bit line pair BP2. A base potential TRB of transistors QRWL1 and QRWL2 and a base potential TRA of transistors QRWR1 and QRWR2 are controlled by a read/write control circuit RWC.
Read/write control circuit RWC controls the base potentials of transistors QRWL1 and QRWL2 and transistors QRWR1 and QRWR2 in response to an external write enable signal WE and input data signal D.sub.IN such that transistors QRWL1 and QRWL2 and transistors QRWR1 and QRWR2 operate in the data reading and data writing as described above.
A data holding current control circuit 7a includes constant current sources IH1 and IH2 connected to negative word lines WN1 and WN2, respectively. Constant current source IH1 holds the storage data of memory cells M11 and M12 by causing a small current to flow to negative word line WN1 at any time. Similarly, constant current source IH2 causes a small current to flow to the other negative word line WN2 at any time to hold the storage data of memory cells M21 and M22.
A word line discharging circuit 7b includes a diode QDD1 having an anode connected to negative word line WN1, a diode QDD2 having an anode connected to the other negative word line WN2, and a constant current source IWDCS. Constant current source IWDCS is connected in common to the cathodes of diodes QDD1 and QDD2. The potentials on negative word lines WN1 and WN2 rise/fall in response to the potential rise/fall of the corresponding positive word lines WP1 and WP2, respectively. Therefore, the change of positive word line WP1 from a selected state to a non-selected state causes the electric charges to be discharged through diode QDD1, whereby the current defined by constant current source IWDCS flows from positive word line WP1 through memory cells M11 and M12 and negative word line WN1 to constant current source IWDCS. As a result, the electric charges stored in positive word line WP1 are extracted at a high speed to rapidly render positive word line WP1 non-selected. The change of positive word line WP2 from a selected state to a non-selected state causes the electric charges to be discharged through diode QDD2. In this case, the electric charges stored in positive word line WP2 are accordingly extracted by constant current source IWDCS at a high speed to rapidly return positive word line WP2 to a non-selected state. As the foregoing, the current flowing for rapidly returning a positive word line to a non-selected state is referred to as a word line discharging current. The arrangement and the operation of word line discharging circuit 7b shown in FIG. 9 is disclosed in more detail in Japanese publication No. 57-17316, for example.
Referring to FIGS. 8 to 10, the data reading operation of the bipolar SRAM will be described. It is assumed in this description that memory cell M11 is selected and storage nodes NR and NL of memory cell M11 are held at a H level and a L level, respectively.
With reference to FIG. 9, when the data is read from memory cell M11, signal X1 in row decoder XT shifts from a H level to a L level in response to an external row address signal at a time t.sub.0. As a result, positive word line WP1 rises to a high potential V.sub.H from a low potential V.sub.NH. Consequently, the potential on negative word line WN1 rises to the potential lower than the potential V.sub.H on positive word line WP1 by a base-to-emitter voltage V.sub.BE of on state transistors QML or QMR in memory cells M11 or M12. In this way, negative word line WN1 enters a selected state out of a non-selected state. As a result, the potential as storage node NR of memory cell M11 rises from the level V.sub.NH of a non-selected state to a level V.sub.H of a selected state as indicated by 1 in FIG. 10. Similarly, the potential at the other storage node NL of memory cell M11 rises from the level V.sub.NL at non-selected state to the level V.sub.L at a selected state as indicated by 2 in FIG. 10.
On the other hand, signals Y1 and Y2 in column decoder YD attain a L level and a H level, respectively, in response to the external column address signal. As a result, bit line selecting signal YS1 attains a H level to select bit line pair BP1, whereby bit line BTL1 is electrically connected to constant current source IRWL and bit line BTR1 is electrically connected to constant current source IRWR. Furthermore, resistor RBC1 is electrically connected to constant current source IBTCL. In this way, bit line pair BP1 enters a selected state out of a non-selected state.
The resistance value of resistor RBC1 is set such that the potential at base node NBC1 is lower than the potential V.sub.L when the current defined by constant current source IBTCL flows to resistor RBC1. Similarly, the resistance value of resistor RBC2 is set to allow the potential at base node NBC2 to be lower than the potential V.sub.L when the current defined by constant current source IBTCL flows to the resistors RBC2. The reason for these resistance values of resistors RBC1 and RBC2 will be explained in the following and therefore no description thereof will be made here.
At the same time, the external write enable signal WE attains a H level.multidot.designating "data reading mode" in the data reading. In response to the H level write enable signal WE, read/write control circuit RWC controls base potentials TRA and TRB of read/write transistors QRWL1 and QRWR1 to become the intermediate potential V.sub.RD between potentials V.sub.L and V.sub.H of storage nodes NL and NR, respectively, of the selected memory cell M11.
The respective transistors of the four transistors each having the emitter connected to bit line BTL1, that is, transistors QRWL1 and QBCL1 and transistors QMLs of memory cells M11 and M21 constitute an ECL for constant current source IRWL. The transistor QML of memory cell M11 having the highest base potential V.sub.H among these four transistors conducts, thereby supplying current to constant current source IRWL. Similarly, transistors QRWR1 and QBCR1 and the respective transistors QMRs of memory cells M11 and M21 constitute an ECL for constant current source IRWR. Therefore, transistor QRWR1 having the highest base potential V.sub.RD among these four transistors conducts, thereby supplying current to constant current source IRWR.
The potential on bit line BTL1 is determined by the base potential of the conducting transistor among the transistors each having the emitter connected to bit line BTL1. Thus, bit line BTL1 attains the potential V.sub.H -V.sub.BE lower than the base potential V.sub.H of transistor QML in memory cell M11 by the base-to-emitter voltage V.sub.BE of the transistor. Similarly, the potential on bit line BTR1 is determined by the base current of the conducting transistor among the transistors connected to BTR1. Thus, bit line BTR1 attains the potential V.sub.RD -V.sub.BE lower than the base potential V.sub.RD of transistor QRWR1 by the base-to-emitter voltage V.sub.BE. As a result, the potential difference V.sub.H -V.sub.RD is produced between the selected bit lines BTL1 and BTR1. The potential difference V.sub.H -V.sub.RD is the potential difference to be sensed by a sense amplifier (not shown).
A writing operation of the bipolar SRAM will be described taking data writing in memory cell M11 as an example. In this description, it is assumed that a L level potential and a H level potential are already held at storage nodes NL and NR of memory cell M11.
Consideration is given to a rewriting of data of memory cell M11, that is, the inversion of the potentials at storage nodes NL and NR of memory cell M11 to a H level and a L level, respectively. In this case, input data terminal T.sub.DI of FIG. 7 receives as an input signal D.sub.IN a data signal corresponding to the data opposite to the data already stored in memory cell M11. The external write enable signal WE is set to a L level designating a "writing mode". Read/write control circuit RWC sets the base potential TRA of read/write transistor QRWR1 (FIG. 10 (4)) to a predetermined potential V.sub.WL lower than the potential V.sub.L, and sets the base potential TRB of read/write transistor QRWL1 (FIG. 10 (3)) to a predetermined potential V.sub.WH higher than the potential V.sub.H in response to the L level write enable signal WE and the input data signal D.sub.IN.
Row decoder XD operates similarly to select positive word line WP1 as in the data reading. As a result, the potential on positive word line WP1 rises to a H level potential V.sub.H. At the same time, column decoder YD operates similarly to select bit line pair BP1 as in the data reading. As a result, bit lines BTL1 and BTR1 constituting bit line pair BP1 are electrically connected to constant current sources IRWL and IRWR, respectively. Then, the base node NBC1 in bit line clamp circuit BTCL is electrically connected to constant current source IBTCL. Just as in the data reading, the potentials as storage nodes NL and NR in memory cell M11 become the potentials V.sub.L and V.sub.H higher than the potentials V.sub.NL and V.sub.NH in the non-selected state, respectively. It is assumed herein that the potential V.sub.L at storage node NL maintaining a L level potential in the selected memory cell M11 is set to be higher than the potential V.sub.NH at the storage node maintaining a H level in the non-selected memory cell M21. In this case, such a relation as follows is established among potentials V.sub.H and V.sub.L of a storage node of a selected memory cell, potentials V.sub.NH and V.sub.NL of a storage node of a non-selected memory cell and the base potentials V.sub.WH and V.sub.WL of reading/writing transistors QRWL1 and QRWR1. EQU V.sub.WH &gt;V.sub.H &gt;(V.sub.RD)&gt;V.sub.L &gt;V.sub.WL &gt;V.sub.NH &gt;V.sub.NL
At this time, irrespective of the held data of memory cell M21, transistor QMR of memory cell M11 has the highest base potential among the transistors each having the emitter connected to bit line BTR1 to constitute the ECL with respect to constant current source IRWR. On the other hand, irrespective of the held data of memory cell M21, reading/writing transistor QRWL1 has the highest base potential among the transistors each having the emitter connected to bit line BTL1 to constitute the ECL with respect to constant current source IRWL. Transistor QMR accordingly conducts in memory cell M11 and transistor QML becomes non-conductive. As a result, the current flows through RMR, thereby lowering the potential at storage node NR after the time t.sub.1 to FIG. 10. Conversely, the electric charge supplied from positive word line WP1 to storage node NL raises the potential at storage node NL after the time t.sub.1 of FIG. 10. Ultimately, the potential at storage node NL rises to the potential V.sub.H on the selected positive word line WP1 which is higher than the potential at storage node NR. In this way, the data of memory cell M11 is rewritten.
As the foregoing, in a conventional bipolar SRAM, the base potentials of transistors QMR and QML of the selected memory cell in a data reading are set to be higher than the base potentials of transistors QMR and QML of the non-selected memory cell having the emitter connected to the same bit line connected to this memory cell. That is, the potential V.sub.L at the storage node maintaining the L level of the selected memory cell is set to be higher than the potential V.sub.NH of the storage node maintaining the H level of the non-selected memory cell. Thus, a margin of a potential difference V.sub.M between the potential V.sub.L and the potential V.sub.NH is required as shown in FIG. 10.
The inversion of the relation between the potential V.sub.L and the potential V.sub.NH (V.sub.L &lt;V.sub.NH is established) causes such a phenomenon as follows.
In writing data different from that already held in an arbitrary memory cell, for example, in writing data to memory cell M11 as described above, transistor QMR of non-selected memory cell M21 has the highest base potential among the transistors constituting the ECL with respect to constant current source IRWL (in a case where memory cell M21 stores the opposite data to the held data in memory cell M11 so that the storage node NL of memory cell M11 has the potential V.sub.NH). Transistor QMR of the non-selected memory cell M21 accordingly conducts and transistor QMR in memory cell M11 which is supposed to conduct becomes non-conductive. As a result, the potential at storage node NR in the selected memory cell M11 does not fall, so that the storage data of the selected memory cell M11 cannot be inverted. In order to avoid such problem, circuit factors should be settled to establish the relation V.sub.L &gt;V.sub.NH between the potentials V.sub.L and V.sub.NH in a data writing. That is, the potential V.sub.NH cannot take the value between the potentials V.sub.N and V.sub.H. It is therefore not possible to set a potential difference V.sub.H -V.sub.NH between a potential on a selected word line and a potential on a non-selected word line to be smaller than a potential difference (referred to as a logical amplitude of a memory cell) V.sub.H -V.sub.L between storage nodes NL and NR of the selected memory cell.
Conversely, correct data reading from a selected memory cell requires one of transistors QML and QMR to be rendered conductive having a base receiving a potential V.sub.H at a storage node NL or NR maintaining a H level of the selected memory cell and of the other to be rendered non-conductive. This requires the potential V.sub.H at the storage node maintaining the H level of the selected memory cell to be higher than the potential V.sub.NH at the storage node maintaining the H level of the non-selected memory cell. This restriction is not so severe as in a data writing. As a result, a difference between the potential at the storage node of the selected memory cell and that at the storage node of the non-selected memory cell is larger than is required in a data reading.
The recent increased capacity of a semiconductor memory device has been followed by an increase in the number of memory cells of the semiconductor memory device. The increase in the number of memory cells means an increase of a total load amount coupled to positive word lines WP1 and WP2 driven by transistors QWD1 and QWD2, respectively in row decoder XD shown in FIG. 9. That is, the parasitic capacitances of the positive word lines WP1 and WP2 with respect to transistors QWD1 and QWD2 are increased. As a result, more time is required of transistors QWD1 and QWD2, respectively. That is more charging time of positive word lines WP1 and WP2 is required. Positive word lines WP1 and WP2 are raised by transistors QWD1 and QWD2, respectively, from the low potential V.sub.NH to the high potential V.sub.H to change from a non-selected state to a selected state. Such an increase in the charging time therefore increases a time period required of positive word lines WP1 and WP2 to change from a non-selected state to a selected state. The charging time of positive word lines WP1 and WP2 also depends on a difference .vertline.V.sub. NH -V.sub.H .vertline. (word line amplitude) between the potential V.sub.NH on positive word lines WP1 and WP2 at a non-selected state and the potential V.sub.H on the same at a selected state. In other words, the larger the word line amplitude is, the longer becomes a time period required of transistors QWD1 and QWD2 to raise the potentials on positive word lines WP1 and WP2 to a predetermined selected potential V.sub.H.
Consideration will be given of a circuit operation in data reading, for example, in reading data from memory cell M11. When the potential at storage nodes NL or NR maintaining the H level in memory cell M11 exceeds the base potential V.sub.RD of reading and writing transistors QRWL1 or QRWR1 in response to the potential rise of the selected positive word line WP1, the transistor conducts which receives, at its base, the potential of the storage node maintaining the H level out of transistors QML and QMR in memory cell M11. As a result, a potential difference is produced between bit lines BTL1 and BTR1, thereby enabling a data reading. A time (access time) required of data to be read from the actually designated memory cell after a memory cell to be selected is designated is accordingly proportional to a time tA1 required of the potential V.sub.NH at the storage node maintaining the H level of the selected memory cell to exceed the reading reference voltage V.sub.RD. The rate of the potential rise of the storage node of the selected memory cell is proportional to the rate of the potential rise of the selected word line. Thus, the longer the time required of positive word lines WP1 and WP2 to enter a selected state from a non-selected state, the more is increased the time tA1, thereby increasing an access time in the data reading.
Therefore, in order to prevent increase of an access time of a bipolar SRAM in consideration of the recent increase in the number of memory cells, a word line amplitude should be reduced. One of prior art for avoiding such an increase in an access time is the technique disclosed in U.S. Pat. No. 4,536,860.